Phase noise is a critical performance parameter of frequency synthesizers for wireless applications. RF system designers of phase modulated cellular systems, such as PHS, GSM and IS-54, need low noise local oscillator (L.O.) or frequency synthesizer blocks. This is a design circuit for the measurement system. This is the figure of the circuit;
The basic phase-lock-loop configuration we will be considering in the figure. The PLL consists of a high-stability crystal reference oscillator, a frequency synthesizer such as the National Semiconductor LMX2332TM, a voltage controlled oscillator (VCO), and a passive loop filter. The crystal reference used is the 10 MHz signal from the back of a spectrum analyzer at about +7 dBm or 1.42 VPP. The VCO used for this test was an ALPS URAE8x934 VCO with a tuning constant of 27 MHz/V phase locked at 900 MHz. By using a relatively wide loop filter bandwidth, (15 kHz for N = 4500) we are able to vary the reference frequency from 30 kHz to 400 kHz without changing the component values and maintain loop stability. The phase noise measurements were made at 150 Hz offset, to ensure that the data was on the flat portion of the curve “inside the loop”. At least 20 video averages were taken over a 1 kHz span for each measurement. In order to come up with the phase noise floor figure of merit the spectrum analyzer measurement must be normalized in terms of dBc/Hz, by subtracting 10 log of the resolution bandwidth used in the measurement. The noise is then referenced to the input of the phase detector by subtracting 20 log N.
[Circuit source: National Semiconductor Notes]
